1. Field of the Invention
The present invention relates to a semiconductor memory device in the form of a shift register. The device according to the present invention is used, for example, for a video RAM in the field of information processing using a computer.
2. Description of the Related Arts
In general, the pointer control portion of a shift register used in connection with a video RAM is supplied with a first and second clock signals S(P1) and S(P2) of different phases. The data "1" in only one element (bit) of the pointer control portion is shifted successively through the elements of the pointer control portion in accordance with the supply of the clock signals S(P1) and S(P2).
In the prior art pointer control portion of a shift register, each element of the pointer control portion must be supplied with the clock signals S(P1) and S(P2). Hence, the structure of each element of the pointer control portion must be complicated.
In the prior art pointer control portion of a shift register, a preparation period is required for each element of the pointer control portion corresponding to a HIGH potential period of the second clock signal S(P2). Hence, the speed of the operation of the pointer control portion is low.
In the prior art pointer control portion of a shift register, the load of the first clock signal S(P1) is different from the load of the second clock signal S(P2). Hence, the structures of the circuits generating the first and second clock signals are complicated.